According to the MEMS technology in recent years, devices in which a sensor, an actuator and the like manufactured by the LSI manufacturing process (semiconductor process) are included have got to be developed.
The size of a chip mounting these devices is various depending on the size of the sensor and actuator to be mounted, and the chip may have a larger area than the normal chip size that is about 1 to 2-cm square or smaller.
In the case of normal LSI chips, probe tests are performed on all of the devices in a wafer state by using a probe card and a test apparatus such as a prober and a tester to discriminate defected chips in the wafer stage in the process prior to a device yield analysis and a subsequent mounting process such as wafer dicing step and packaging step.
Probe test is performed by putting needles on all of pads to which power and signals from the external are supplied by using a probe card to detect defects in electrical characteristics of the devices on the chip, and further detects defects in the pad itself.
To perform a probe test, a probe card having a needle arrangement same as a pad arrangement of respective chips, a mother board for attaching the probe card to a prober and tester, and a holder for holding the probe card and the mother board are required.
In the case where the chip has the size of normal LSI chips, the mother board and holder are common and shared to use, and the probe test can be performed when preparing probe cards corresponding to respective chips. In other words, when performing probe tests on chips of a plurality of product classes by a prober and a tester, change of the test apparatus is done only by exchanging the probe cards. And thus, probe tests can be performed by measuring programs corresponding to respective kinds of chips, thereby preventing lowering of throughput in test.
For example, Japanese Patent Application Laid-Open Publication No. 2002-303653 (Patent Document 1) discloses a technique of an arrangement where the pads to be used in a probe test are collected on two sides of the four sides of outer circumference of a chip, thereby easing the needle-putting of the probe card and enabling tests on a neighboring plurality of chips at the same time.
And, Japanese Patent Application Laid-Open Publication No. H8-64648 (Patent Document 2) discloses a technique of providing a probe test pad to be shared by a neighboring plurality of chips and using a decoder circuit to select chips to be tested, thereby enabling tests on the plurality of chips by one time of needle-putting.
Moreover, Japanese Patent Application Laid-Open Publication No. H7-176577 (Patent Document 3) discloses a technique of sectioning one chip into a plurality of areas and performing probe tests on respective areas at the same time, thereby shortening test time.